This application claims benefit of priority under 35 USC xc2xa7119 to Japanese Patent Applications No. 2000-174127, filed on Jun. 9, 2000, and 2001-171612, filed on Jun. 6, 2001, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
This invention relates to a semiconductor memory integrated circuit made up of a cell array with an arrangement of electrically erasable and programmable nonvolatile memory cells and a transistor circuit disposed around the cell array (peripheral circuit), and a manufacturing method of the semiconductor memory integrated circuit.
2. Description of the Related Art
Memory cells of EEPROM flash memory has a transistor structure including stacked floating gates and control gates. The floating gate of such a memory cell is commonly made of a polycrystalline silicon film doped with phosphorus to an adequate concentration. Phosphorus concentration of the floating gate affects the quality of an underlying tunnel insulating film and the configuration of the floating gate itself by post thermal oxidation. Since the quality of the tunnel insulating film and the floating gate configuration significantly influence the property and reliability of the memory cell, they need be properly controlled independently from other parameters.
On the other hand, the transistor circuit disposed around the cell array (hereinbelow simply called peripheral circuit) is made by using a CMOS structure at least in a logic circuit. To ensure that transistors of the peripheral circuit exert their performance required as surface channel type transistors, it is necessary to dope a p-type impurity (typically boron) into gate electrodes in case of MOS transistors or an n-type impurity (typically arsenic) into gate electrodes in case of NMOS transistors. Additionally, to prevent depletion of gates, a doped amount not less than a predetermined concentration and activation of the impurity are indispensable.
Taking account of these requirements for such a cell array and its peripheral circuit, for conventional flush memory, the following manufacturing process is used. FIGS. 35(a) through 35(d) show major steps noticing the cell array region. As shown in FIG. 35(a), a silicon substrate 1, having formed a tunnel oxide layer 2 thereon and a polycrystalline silicon film 3a on the tunnel oxide layer 2, is separated into respective device regions by STI (shallow trench isolation) technology. That is, device isolation grooves 4 are made by RIE, and they are buried with a device isolation insulation film 5 as shown in FIG. 35. The polycrystalline silicon film 3a will serve as a base layer of floating gates.
This method of first stacking the polycrystalline Si film as a part of the floating gates and thereafter making a groove-like device isolation regions into the Si substrate is a technique very effective for miniaturizing memory cells while alleviating variance of electrical properties of the memory cells. The method of making floating gates after making the device isolation regions is liable to be affected by concentration of an electric field near the device isolation regions, and also liable to invite variance in the amount of capacitance coupling between the floating gates and the Si substrate. To prevent these problems, the use of a process unsuitable for miniaturizing memory cells is compelled.
Next stacked is a polycrystalline silicon film 3b which will form an upper layer of the floating gates. Let the polycrystalline silicon film 3b be doped with phosphorus. As a result, in a later thermal step, phosphorus diffuses from the polycrystalline silicon film 3b into the underlying polycrystalline silicon film 3a, and it results in uniformly doping the impurity into the floating gates in form of a multi-layered film. At that time, doping of a proper concentration of phosphorus will round corners of the floating gates in a post oxidation step, and it will function to prevent concentration of the electric field to edges of the floating gates during write and erase operations.
Excessively high phosphorus concentration of the floating gates will adversely affect the tunnel oxide film 2 under the floating gates. Excessively low phosphorus concentration will leave lower corners of the floating gates square, and will invite concentration of the electric field. This will cause variance and deterioration in reliability of write, erase and other properties of the memory cells. Therefore, proper control of the phosphorus concentration in the floating gates is important for flash memory. If arsenic is used as the impurity of the floating gates, corner rounding by thermal oxidation is not expected unlike the use of phosphorus, and phosphorus is used preferably.
After the step of FIG. 35(C), the polycrystalline silicon film 3b is selectively etched to separate the film of the floating gates into cell regions, and thereafter, a gate insulation film 6 is formed and a polycrystalline silicon film 7 is stacked to form control gates. Commonly used as the gate insulating film 6 is a composite film (ONO film) of oxide/nitride/oxide layers.
Next directing to the peripheral circuit, in the status where the gate insulating film 6 is formed in the cell array region, in the peripheral circuit region, the gate insulating film is removed by etching, the polycrystalline silicon films 3a, 3b are also removed, and the tunnel oxide film is removed as well. Then, after an appropriate gate oxide film is formed to comply with a resistance to pressure necessary for the respective transistor regions, a polycrystalline silicon film 7 used as control gates in the cell array region will be stacked. That is, by patterning the polycrystalline silicon film 7, control gates in the cell array region and gated electrodes of transistors in the peripheral circuit are formed simultaneously.
After the control gates of the cell array and gate electrodes of the peripheral circuit are made, an n-type impurity is ion-implanted into the cell array region and the NMOS transistor regions of the peripheral circuit, and a p-type impurity is additionally ion-implanted into the PMOS transistor regions of the peripheral circuit. As a result, source and drain diffusion layers of the cell array region and the peripheral circuit region are formed, the n-type impurity is doped into the control gates of the cell array region and the gate electrodes of the NMOS transistor in the peripheral circuit, and the p-type impurity is doped into the gate electrodes of the PMOS transistor in the peripheral circuit.
In the conventional process reviewed above, the peripheral circuit region needs removing the tunnel oxide film formed over both the peripheral circuit region and the cell array region, newly forming a gate oxide film for high-voltage circuit transistors, then selectively removing the gate oxide film by etching and thereafter forming a gate oxide film for low-voltage circuit transistors. Repeating such etching steps of oxide films several times causes, in the peripheral circuit region, retraction of the device isolation insulating film already buried. FIG. 36(a) shows an aspect of such retraction. If the gate oxide film 8 is formed as shown in FIG. 36(b) on the structure shown in FIG. 36(a) to make gate electrodes 9, edge portions of the gate electrodes 9 enter into the concave portions of the device isolation insulating film in contact with side surfaces of device regions as shown by the broken line A.
Configuration as shown in FIG. 36(b) invites a short-channel effect opposite to a normal short-channel effect (opposite short-channel effect), in which the threshold value lowers when the peripheral circuit transistors are short-channeled. Also invited are an increase of the leak current of the peripheral circuit transistors, deterioration of their sub-threshold characteristics and, hence, increase of the standby current in the peripheral circuit. Further, deterioration of the reliability of the gate insulating film at end portions of the gate electrodes is also invited.
It is therefore an object of the invention to provide a semiconductor memory integrated circuit and its manufacturing method that improve property and reliability of a peripheral circuit.
According to one aspect of the invention, there is provided a semiconductor memory integrated circuit comprising:
a semiconductor substrate;
a device isolation insulating film buried in grooves formed into the semiconductor substrate;
a cell array having an arrangement of electrically erasable and programmable nonvolatile memory cells made by stacking floating gates and control gates on the semiconductor substrate; and
a peripheral circuit disposed around the cell array on the semiconductor substrate,
at least the bottom layer of the floating gates of the nonvolatile memory cells and at least the bottom layer of gate electrodes of transistors in the peripheral circuit being stacked before the device isolation insulating film is buried, then being maintained in self alignment with the device isolation insulating film, and impurities being doped thereto under different conditions from each other.
According to another aspect of the invention, there is provided a method of manufacturing a semiconductor memory integrated circuit comprising the steps of:
forming a plurality of gate insulating films each having a thickness required for each of a cell array region and a peripheral circuit region on a semiconductor substrate;
stacking a first-layer gate electrode material film not doped with impurities on the gate insulating films;
etching the semiconductor substrate covered with the first-layer gate electrode material film to make grooves for device isolation, and burying the device isolation grooves with a device isolation insulating film;
stacking a second-layer gate electrode material film not doped with impurities on the first-layer gate electrode material film maintained in self alignment with regions surrounded by the device isolation insulating film and on the device isolation insulating film;
selectively introducing impurities into the first-layer and second-layer gate electrode material films in the cell array region;
selectively etching the second-layer gate electrode material film to separate same on the device isolating insulating film in the cell array region;
forming a gate insulating film on the second-layer gate electrode material film to serve as an insulation film between floating gates and control gates of memory cells;
removing the gate insulating film from the peripheral circuit region;
stacking a third-layer gate electrode material film not doped with impurities on the gate insulating film;
processing the gate electrode material in the memory cell region and the peripheral circuit region into a desired pattern to form control gate and floating gates in the memory cell region and form gate electrodes in the peripheral circuit region; and
forming source and drain diffusion layers and lowering the resistance of the gate electrodes by introducing impurities into the memory cell region and the peripheral circuit region under a plurality of different conditions.
In the manufacturing method described above, as far as the cell array region is concerned, floating gates can be also made solely of the first-layer gate electrode material film without stacking the second-layer gate electrode material film.
According to a further aspect of the invention, there is provided a method of manufacturing a semiconductor memory integrated circuit comprising the steps of:
forming a plurality of gate insulating films each having a thickness required for each of a cell array region and a peripheral circuit region on a semiconductor substrate;
stacking a first-layer gate electrode material film not doped with impurities on the gate insulating films;
etching the semiconductor substrate covered with the first-layer gate electrode material film to make grooves for device isolation, and burying the device isolation grooves with a device isolation insulating film;
stacking a second-layer gate electrode material film not doped with impurities on the first-layer gate electrode material film maintained in self alignment with regions surrounded by the device isolation insulating film and on the device isolation insulating film;
selectively introducing impurities into the first-layer and second-layer gate electrode material films in the cell array region;
selectively etching the second-layer gate electrode material film to separate same on the device isolating insulating film in the cell array region;
forming a gate insulating film on the second-layer gate electrode material film to serve as an insulation film between floating gates and control gates of memory cells;
stacking a third-layer gate electrode material film on the gate insulating film;
removing the third-layer gate electrode material film from the peripheral circuit region;
processing the gate electrode material in the memory cell region and the peripheral circuit region into a desired pattern to form control gates and floating gates in the memory cell region and form gate electrodes in the peripheral circuit region; and
forming source and drain diffusion layers and lowering the resistance of the gate electrodes by introducing impurities into the memory cell region and the peripheral circuit region under a plurality of different conditions.
According to a still further aspect of the invention, there is provided a method of manufacturing a semiconductor memory integrated circuit comprising the steps of:
forming a plurality of gate insulating films each having a thickness required for each of a cell array region and a peripheral circuit region on a semiconductor substrate;
stacking a first-layer gate electrode material film not doped with impurities on the gate insulating films;
selectively etching the semiconductor substrate covered with the first-layer gate electrode material film to form device isolation grooves, and burying the device isolation grooves with a device isolation insulating film;
forming a barrier film on the device isolation insulating film and the first-layer gate electrode material film maintained in self-alignment in regions surrounded by the device isolation insulating film to prevent diffusion of impurities;
selectively removing the barrier film from above the cell array region;
stacking on the entire surface a second-layer gate electrode material film doped with impurity;
selectively etching the second-layer gate electrode material film to remove the second-layer gate electrode material film from above the device isolation insulation film within the cell array region, and removing the second-layer gate electrode material film from the peripheral circuit region;
stacking a third-layer gate electrode material film not doped with impurities on the cell array region having the gate insulating film selectively formed on the second-layer gate electrode material film and on the peripheral circuit region from which the barrier film has been removed;
selectively etching the first-layer and third-layer gate electrode material films to form control gates and floating gates in the cell array region and gate electrodes in the peripheral circuit region; and
forming source and drain diffusion layers and lowering the resistance of the gate electrodes by introducing impurities into the memory cell region and the peripheral circuit region under a plurality of different conditions.
According to a yet further aspect of the invention, there is provided a method of manufacturing a semiconductor memory integrated circuit comprising the steps of:
forming a plurality of gate insulating films each having a thickness required for each of a cell array region and a peripheral circuit region on a semiconductor substrate;
stacking a first-layer gate electrode material film not doped with impurities on the gate insulating films;
selectively etching the semiconductor substrate covered with the first-layer gate electrode material film to form device isolation grooves, and burying the device isolation grooves with a device isolation insulating film;
doping an impurity into the first-layer gate electrode material film on the cell array region;
etching the entire surface of the device isolation insulating film projecting upward to a level exposing side surfaces of the first-layer gate electrode material film;
forming a gate insulating film to cover the first-layer gate electrode material film;
stacking a second-layer gate electrode material film over the entire surface;
selectively etching the first-layer and second-layer gate electrode material films to form control gates and floating gates in the cell array region and gate electrodes in the peripheral circuit region; and
forming source and drain diffusion layers and lowering the resistance of the gate electrodes by introducing impurities into the cell array region and the peripheral circuit region under a plurality of different conditions.
According to a yet further aspect of the invention, there is provided a method of manufacturing a semiconductor memory integrated circuit comprising the steps of:
forming a plurality of gate insulating films each having a thickness required for each of a cell array region and a peripheral circuit region on a semiconductor substrate;
stacking a first-layer gate electrode material film not doped with impurities on the gate insulating films;
selectively etching the semiconductor substrate covered with the first-layer gate electrode material film to form device isolation grooves, and burying the device isolation grooves with a device isolation insulating film;
forming a barrier film on the device isolation insulating film and the first-layer gate electrode material film maintained in self-alignment in regions surrounded by the device isolation insulating film to prevent diffusion of impurities;
selectively removing the barrier film from above the cell array region;
stacking on the entire surface a second-layer gate electrode material film doped with impurity;
removing the entire surface of the second-layer gate electrode material film to the level of and exposing the top surface of the device isolation insulating film in the cell array region;
removing the second-layer gate electrode material film from the peripheral circuit region;
etching the entire surface of the device isolation insulating film projecting upward to a level exposing side surfaces of the first-layer gate electrode material film;
forming a gate insulating film to cover the second-layer gate electrode material film on the cell array region;
stacking a third-layer gate electrode material film on the entire surface;
selectively etching the first-layer to third-layer gate electrode material films to form control gates and floating gates in the cell array region and gate electrodes in the peripheral circuit region; and
forming source and drain diffusion layers and lowering the resistance of the gate electrodes by introducing impurities into the cell array region and the peripheral circuit region under a plurality of different conditions.
The present invention ensures impurity doping individually optimum for floating gates and control gates of memory cells, and gate electrodes of the peripheral circuit. In addition, At least the bottom layer of gate electrodes in the cell array region and the peripheral circuit region is stacked before the device isolation insulating film is buried, and remains in self-alignment with the device isolation insulating film. Therefore, unlike the process of making gate insulating films different in thickness through a plurality of etching steps of oxide films after burying the device isolation insulating film, here is prevented retraction of the device isolation insulating film in the peripheral circuit region, and property and reliability of the peripheral circuit transistors can be improved.